Etched
Physical Design Engineer - Block Level, Subsystem Implementation
About this role
Etched seeks a Physical Design Engineer to own block-level and subsystem implementation for AI inference accelerator chips, from synthesis through GDSII sign-off. You'll optimize power, performance, and area while collaborating with RTL designers and managing closure across advanced process nodes.
What you'll do
- Lead end-to-end block physical design including floorplanning, synthesis, placement, clock tree synthesis, and routing
- Drive timing closure across all corners and modes with constraint development and ECO implementation
- Complete signoff tasks: EM analysis, IR drop, RC extraction, DRC, LVS, and antenna verification
- Generate timing budgets, abstracts, and hierarchical integration views for top-level assembly
- Collaborate with RTL teams to provide physical design feedback for PPA improvements
- Oversee third-party physical design work and ensure quality of delivered blocks
What they're looking for
- RTL-to-GDSII design flow and methodology
- Cadence Innovus/Genus or Synopsys Fusion Compiler
- Timing closure and STA tools (PrimeTime, Tempus)
- Power analysis and UPF-based low power design
- Advanced process node experience (5nm and below)
- Tcl, Python, or Perl scripting for automation
- IR drop, EM analysis, and physical verification
- Floorplanning, placement, clock tree, and routing
Benefits
- Medical, dental, and vision coverage with generous premiums
- $500/month credit for waiving medical benefits
- $2,000/month housing subsidy for those near the office
- Relocation support to San Jose
- Wellness benefits including fitness and mental health
- Daily lunch and dinner provided at office
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Etched
Etched builds AI inference hardware, designing and manufacturing complex mechanical and electrical components for data center systems. The company is hiring mechanical engineers, PCB designers, hardware verification engineers, and software engineers to develop manufacturing processes, circuit boards, verification infrastructure, and internal tools across its hardware and operations.
- Website
- etched.com
Likely interview questions
- Walk us through your experience closing timing on an advanced process node—what were the biggest challenges and how did you overcome them?
- Describe a time you had to debug a complex timing or physical verification issue; what was your approach?