Etched
Physical Design Engineer - Full Chip Implementation
About this role
Etched seeks an experienced Physical Design Engineer to lead full-chip implementation for AI inference hardware, managing all aspects from floorplanning and place-and-route through GDSII sign-off on advanced process nodes. You will drive timing closure, physical verification, and collaborate with RTL teams to optimize PPA and accelerate time-to-market for next-generation AI infrastructure.
What you'll do
- Own full-chip clocking strategy across all PVT corners and operating modes
- Manage MMMC timing closure and hierarchical timing budgeting between top-level and block designs
- Drive ECO closure and achieve final timing sign-off for tapeout readiness
- Lead physical verification at block, subsystem, and full-chip levels (DRC, LVS, ERC, antenna, density)
- Debug and fix complex PV violations directly in layout using Innovus
- Build repeatable, tapeout-ready PV methodology with clean runs and rigorous signoff reviews
What they're looking for
- Full-chip physical design and floorplanning on advanced nodes (5nm and below)
- Cadence Innovus, Genus, or Synopsys Fusion Compiler RTL-to-GDSII flows
- Synopsys PrimeTime and Cadence Tempus timing signoff
- Pegasus or Calibre physical verification signoff
- Hierarchical timing budgeting and constraint management
- Python or scripting language for automation
- Understanding of ML/LLM architectures (preferred)
- Startup environment adaptability and first-principles problem solving
Benefits
- Medical, dental, and vision coverage with generous premiums
- $500 monthly credit for waiving medical benefits
- $2,000 monthly housing subsidy for office-proximate residents
- Relocation support to San Jose
- Wellness benefits including fitness and mental health programs
- Daily lunch and dinner at office; unlimited compute budget with ROI justification
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Etched
Etched builds AI inference hardware, designing and manufacturing complex mechanical and electrical components for data center systems. The company is hiring mechanical engineers, PCB designers, hardware verification engineers, and software engineers to develop manufacturing processes, circuit boards, verification infrastructure, and internal tools across its hardware and operations.
- Website
- etched.com
Likely interview questions
- Walk us through your approach to hierarchical timing budgeting on a complex multi-block design—how do you manage constraints between top-level and sub-blocks?
- Describe a challenging physical verification closure you've navigated; what was the root cause and how did you systematically resolve it?