Etched.ai

Post-Silicon Validation Engineer

San Jose$160k–$260kfulltimemidAdded today

About this role

Etched is seeking a Post-Silicon Validation Engineer to lead ASIC bring-up, debug, and characterization for AI/ML accelerator hardware. You'll own early silicon validation, perform deep-dive troubleshooting across multiple abstraction levels, and develop automation frameworks to ensure functional correctness and performance through production ramp.

What you'll do

Drive first silicon bring-up including boot, initialization, and ASIC debug
Perform root-cause analysis of silicon issues at RTL, firmware, and system levels
Validate and characterize custom IP blocks and accelerator components
Develop post-silicon validation infrastructure, automation, and test suites
Execute functional, performance, and stress testing with corner case analysis
Use lab instrumentation for signal characterization and system validation

What they're looking for

Post-silicon validation and ASIC bring-up (7+ years)
C, Python, and scripting for test automation
Oscilloscopes, logic analyzers, and protocol analyzers
Firmware, bootloaders, and low-level debug environments
Peripheral interfaces (I2C, SPI, UART, JTAG, PCIe, Ethernet)
Memory subsystems (HBM, DDR)
AI/ML accelerator experience preferred
Strong cross-team collaboration and problem-solving

Benefits

Medical, dental, and vision coverage with $500/month credit option
$2k/month housing subsidy for local residents
Relocation support to San Jose
Wellness benefits including fitness and mental health
Daily lunch and dinner in office
Unlimited compute budget subject to ROI justification

Likely interview questions

Walk us through your experience bringing up first silicon. What were the most critical issues you encountered during early boot and initialization, and how did you debug them?
Describe your hands-on experience with lab instrumentation like oscilloscopes, logic analyzers, and protocol analyzers. Which interfaces have you debugged most frequently?

Tell us about a time you had to collaborate across RTL, firmware, and board teams to root-cause a silicon issue. How did you approach the problem?
What experience do you have validating and characterizing accelerator components or compute units? How did you define coverage metrics?
Describe your proficiency with C and Python in the context of validation automation. Have you built test suites, regression frameworks, or result analysis tools?
Have you worked with high-speed protocols like PCIe or Ethernet, or memory subsystems like HBM/DDR? What validation challenges did you face?
Tell us about a test escape or silicon errata you identified. How did you communicate findings and influence firmware workarounds or future silicon revisions?

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