MatX
SOC Integration Engineer
Mountain View, CAmidAdded 1 week ago
About this role
MatX is looking for a SOC Integration Engineer to enhance their silicon architecture for AGI solutions. The role involves collaborating with various teams to integrate subsystems into SOC designs, automate RTL processes, and ensure timing performance in silicon products.
What you'll do
- Develop scalable integration methodologies for SOC designs
- Collaborate with subsystem owners for SOC integration
- Implement automation processes for SOC RTL generation
- Work with Physical Design teams on chip layout requirements
- Define SOC-level timing constraints and validation processes
- Support package and board teams with SOC requirements
What they're looking for
- Proficiency in SystemVerilog and scripting languages (Python, Perl)
- Experience integrating high-performance computing elements
- Knowledge of logical equivalency verification methods
- Expertise in memory wrapper generation and DFT integration
- Automation for SOC RTL configuration and generation
- Experience with design synthesis and timing constraints
- Familiarity with emulation platforms and verification
- Hands-on experience with AI-driven design tools
Benefits
- Flexible equity compensation options
- Health, dental, vision, and life insurance
- Generous paid time off and company holidays
- Paid parental leave up to 12 weeks
- Professional development allowance of $1,500 annually
- 401K with 5% company contribution
Opens the official application on the employer’s site. No login required.
MatX
MatX builds cutting-edge AI silicon and the system software stack to power it, focusing on optimizing hardware and software for large-scale machine learning workloads. The company is hiring system software engineers, kernel developers, compiler engineers, hardware simulators, and SOC integration engineers to design high-performance AI compute platforms.
View all jobs at MatXLikely interview questions
- Walk us through your experience integrating high-performance computing elements like CPUs, GPUs, or accelerators into SOC designs. What challenges did you encounter and how did you resolve them?
- Describe your hands-on experience with SystemVerilog and scripting languages for SOC RTL design. Can you give an example of automation you've built for RTL integration or generation?