ASIC/SOC DFT Engineer (Silicon Engineering)

About this role

SpaceX seeks an ASIC/SOC DFT Engineer to develop next-generation chips for Starlink satellites and ground infrastructure. You'll work on scan insertion, DFT integration, ATPG analysis, and gate-level simulation to ensure high-quality test coverage in space-deployed silicon.

What you'll do

• Evaluate design readiness and run Scan Design Rule Checks (DRC) through RTL and physical design tools
• Integrate and verify Design for Test (DFT) fabrics and IP blocks within subsystems
• Execute scan insertion via synthesis tools and optimize recipes for maximum test coverage
• Perform ATPG analysis to validate scan chain quality and coverage goals
• Run and debug gate-level simulations with SDF annotation for timing accuracy
• Collaborate with physical design, ATPG, and manufacturing teams to achieve high scan coverage in production silicon

What they're looking for

• ASIC design flow and methodologies
• Scan insertion and DFT setup
• ATPG (Automatic Test Pattern Generation) tools and analysis
• Verilog/SystemVerilog for design block integration
• Scripting (csh/bash, Perl, Python)
• UPF (Unified Power Format) and formal verification
• Gate-level simulation and debugging
• Physical design and DRC rule checking

Benefits

• Medical, vision, and dental coverage
• 401(k) retirement plan with company match eligibility
• Long-term incentives (stock or cash awards) and ESPP stock purchase discount
• Paid parental leave, short/long-term disability, and life insurance
• 3 weeks paid vacation and 10+ paid holidays annually
• Paid sick leave per company policy