Design Verification Engineer (Silicon Engineering)

About this role

SpaceX seeks a Design Verification Engineer to develop and validate next-generation ASICs for Starlink satellite and ground infrastructure. You'll lead digital verification efforts across block and system levels, create comprehensive testbenches in SystemVerilog, and support the full chip lifecycle from pre-silicon through post-silicon validation.

What you'll do

• Perform digital ASIC verification at block and system level
• Develop and maintain SystemVerilog testbench infrastructure using UVM and non-UVM methodologies
• Write test plans, design test harnesses, and execute test sequences with regression analysis
• Close code and functional coverage metrics and manage test case execution
• Automate test generation using Python and MATLAB for complex designs including DSP blocks
• Support pre-silicon verification, chip bring-up, and post-silicon validation activities

What they're looking for

• SystemVerilog and UVM verification methodologies
• Digital ASIC verification and testbench development
• Python and MATLAB scripting for test automation
• Constrained random verification techniques
• Coverage modeling and test plan development
• RTL design understanding and chip bring-up experience
• Object-oriented programming
• Problem-solving and debugging in complex digital systems

Benefits

• Comprehensive medical, vision, and dental coverage
• 401(k) retirement plan with company stock purchase options
• 3 weeks paid vacation and 10+ paid holidays annually
• Short and long-term disability and life insurance
• Paid parental leave and 5 days annual sick leave
• Long-term incentives including stock options and performance bonuses