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SpaceX

New Graduate Engineer, Silicon Engineering

Irvine, CAfull-timeentryAdded today

About this role

SpaceX is hiring new graduate engineers to develop next-generation silicon for Starlink, working across ASIC/FPGA design, RF/analog IC, digital signal processing, and physical design. You'll participate in all phases of silicon development from pre-silicon through post-silicon validation using advanced tools and methodologies.

What you'll do

  • Participate in ASIC/FPGA design and verification flows, including architecture, RTL implementation, and emulation
  • Bring-up and validate ASICs and FPGAs in the lab using C/C++ and Python
  • Simulate RF/analog IC systems and derive specifications for RFIC subsystems and circuits
  • Develop RTL designs in SystemVerilog for DSP and digital communication blocks
  • Perform synthesis, floor planning, place and route, timing analysis, and physical verification
  • Participate in silicon tapeouts for advanced technology nodes

What they're looking for

  • ASIC/SOC/FPGA design and verification
  • SystemVerilog, Verilog, VHDL, C/C++
  • Python for automation and scripting
  • RF/analog CMOS IC design and physical design
  • Simulation tools (ADS, Spectre, HFSS, Momentum)
  • Digital signal processing
  • RTL design and chip bring-up
  • Computer architecture understanding
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SpaceX

SpaceX develops advanced spacecraft and satellite systems, including the Starshield government satellite constellation and Starfall re-entry cargo capsule for global delivery. The company is hiring engineers in avionics integration, software test automation, mechanical design, and hardware reliability to validate flight-critical systems and ensure mission success.

Website
spacex.com
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Likely interview questions

  • Walk us through a complex digital design you've verified end-to-end—what challenges did you face and how did you overcome them?
  • Describe your experience with SystemVerilog or Verilog RTL design. How have you approached testbench development and simulation?