ALTEN Technology USA
Embedded Software Engineer (PL Integration & IPC)
About this role
Lead AMD Versal SoC bring-up for an infotainment platform, focusing on programmable logic integration and inter-processor communication between Versal cores and AMD APU. This role involves FPGA driver development, BSP implementation, and real-time performance validation across heterogeneous compute boundaries.
What you'll do
- Bring up AMD Versal SoC on custom board, transitioning from EVK reference design
- Develop and validate programmable logic integration including IP instantiation, AXI interfaces, and configuration
- Implement and validate inter-processor communication mechanisms (RPMsg, OpenAMP, shared memory) between Versal AI/RPU and AMD APU
- Develop board support packages and drivers for Versal PS subsystems (RPU and APU partitions)
- Validate real-time latency and data throughput across PL–PS–APU boundary
- Create and validate sample applications demonstrating PL IP integration and Versal/x86 interfaces
What they're looking for
- AMD Versal or Zynq UltraScale+ SoC bring-up
- FPGA/PL driver integration and AXI interconnect configuration
- Inter-processor communication (RPMsg, OpenAMP, shared memory)
- Petalinux and Yocto BSP development
- C/C++ and Python/Rust programming
- Xilinx/AMD Vitis HLS and SDK toolchain
- Hardware debugging and Xilinx debug tools
- Real-time performance analysis and validation
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ALTEN Technology USA
ALTEN Technology USA provides engineering validation, testing, and technical support services for automotive systems including connected vehicles, propulsion controls, infotainment, battery systems, and power electronics. The company is hiring validation engineers, test engineers, design engineers, and issue resolution specialists to develop test plans, verify compliance, investigate technical issues, and support product development across automotive hardware and software platforms.
View all jobs at ALTEN Technology USALikely interview questions
- Walk us through your most complex Versal or Zynq UltraScale+ bring-up project—what were the biggest challenges you faced with PL integration?
- How have you implemented and debugged inter-processor communication (RPMsg or OpenAMP) between heterogeneous processors? What latency or throughput issues did you encounter?