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Cesium Astro

FPGA Engineer I

Melbourne, FLfull-timeentryAdded today

About this role

CesiumAstro seeks an FPGA Engineer I to design and verify hardware for satellite and aerospace communication systems. You'll work on high-speed digital circuits, serial interfaces, and signal processing cores throughout the full development lifecycle in a startup environment.

What you'll do

  • Design and implement FPGA circuits using HDL (Verilog/VHDL) for aerospace applications
  • Develop high-speed serial interfaces, data streams, and digital processing cores
  • Perform verification, testing, and validation of FPGA designs using simulation tools
  • Manage complex multi-clock domain designs and hardware control interfaces
  • Conduct lab testing with oscilloscopes, spectrum analyzers, and signal measurement equipment
  • Collaborate with cross-functional teams on satellite and spacecraft communication systems

What they're looking for

  • FPGA design with Verilog or VHDL
  • Xilinx Vivado and simulation tools (ModelSim or equivalent)
  • HDL verification methodologies
  • High-speed digital circuit design
  • Lab instrumentation (oscilloscope, spectrum analyzer, signal generators)
  • Digital signal processing
  • Board-level hardware design
  • Aerospace systems knowledge

Benefits

  • Company stock options
  • Health, dental, and vision insurance
  • HSA and FSA accounts
  • Life and disability insurance
  • Retirement plans
  • Dynamic startup work environment
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Cesium Astro

Cesium Astro develops advanced hardware and systems for aerospace applications including satellites, UAVs, and rocket propulsion platforms. The company is hiring for specialized engineering roles including FPGA engineers, wire harness designers, turbomachinery engineers, and software project engineers to support its satellite and spacecraft development.

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Likely interview questions

  • Walk us through a complex FPGA design you've implemented—what were the challenges with clock domain crossings or high-speed interfaces?
  • How do you approach verification and testbench development for HDL designs, and what tools have you used?
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