Physical Design Engineer

About this role

Etched seeks an experienced Physical Design Engineer to lead block-level chip implementation and optimization for AI inference hardware. You'll drive timing closure, manage design flows, collaborate with RTL teams, and oversee third-party design work while helping scale the company's design infrastructure.

What you'll do

• Own block-level physical design implementation and verification through GDSII sign-off
• Drive timing closure and PPA optimization while maintaining convergence dashboards
• Collaborate with RTL designers to provide feedback and improve design performance
• Supervise and manage third-party physical design outsourcing
• Automate and optimize EDA tool flows in coordination with vendors
• Support ASIC infrastructure and improve CAD tools and design methodology

What they're looking for

• 5-10+ years physical design experience on advanced nodes (5nm and below)
• Cadence (Innovus, Genus) or Synopsys (ICC2, Fusion Compiler) tools
• Sign-off tools (PrimeTime, Tempus, Voltus)
• UPF-based low power design, timing closure, and floorplanning/placement/routing
• Python or scripting language for flow automation
• Formal verification, scan insertion, IR drop, and EM/antenna analysis
• Knowledge of ML/LLM architectures (preferred)
• First-principles problem-solving and creative thinking

Benefits

• Medical, dental, and vision insurance with generous coverage ($500/month credit option)
• $2,000/month housing subsidy for office-proximate employees
• Relocation support to San Jose (Santana Row)
• Daily lunch and dinner provided in office
• Wellness benefits covering fitness and mental health
• Unlimited compute budget subject to ROI justification

Likely interview questions

• Walk us through your experience with RTL-to-GDSII flows using Cadence or Synopsys tools. What were the biggest challenges you faced in timing closure on advanced nodes?
• Describe a time when you optimized PPA for a block. What tradeoffs did you make and how did you validate your decisions?