IC/RTL Design Engineer

About this role

Design and implement high-speed digital RTL for the front-end datapath of a chip, connecting UCIe and optical interfaces. You'll own blocks from micro-architecture through verification, writing clean, timing-aware SystemVerilog while collaborating across architecture, DV, and backend teams.

What you'll do

• Develop block-level micro-architecture and RTL implementation in SystemVerilog for datapath, adapters, and FIFOs
• Write lint-clean, CDC/RDC-clean RTL following coding standards and manage clock-gating and pipelining for power/timing
• Create block-level testbenches, SVA assertions, and sanity checks before handing off to design verification
• Integrate IP blocks, support parameterization, and ensure blocks meet configurability requirements
• Partner with backend team on timing closure, synthesis, and physical design of assigned blocks
• Support bring-up, debug, and silicon validation across simulation, emulation, and FPGA prototyping environments

What they're looking for

• SystemVerilog RTL design (3+ years)
• Digital design fundamentals: pipelining, FSMs, FIFOs, CDC, streaming interfaces
• Lint and CDC/RDC compliance; clean RTL practices
• Power and timing analysis; synthesis and timing closure
• SVA assertion-based verification
• Python, Perl, or TCL scripting for debug and automation
• High-speed datapath or interface design (UCIe, PCIe preferred)
• Simulation debug and waveform analysis