OpenAI
Hardware Tools Engineer
About this role
OpenAI seeks a Hardware Tools Engineer to build and maintain the software tooling ecosystem that enables the hardware team to design next-generation AI-native silicon. You'll develop compilers, IR transformations, simulation, debugging, and automation infrastructure while collaborating with architects and RTL designers to solve real engineering challenges.
What you'll do
- Build and improve hardware compilation, IR transforms, RTL generation, simulation, and automation tooling
- Extend compiler stacks including frontends, IR passes, lowering, scheduling, and Verilog/SystemVerilog codegen
- Enhance developer experience through reproducible builds, better error messages, and faster iteration loops
- Read and debug Verilog/SystemVerilog to validate tool output and improve debuggability
- Work with designers and verification engineers to translate engineering friction into scalable solutions
- Enable PPA optimization by building analysis tools around area, timing, and power tradeoffs
What they're looking for
- Software development in Rust, C++, or Python
- Strong CS fundamentals (data structures, algorithms, debugging, design)
- Digital design concepts and ability to read RTL/Verilog/SystemVerilog
- Compiler and IR concepts (representations, passes, transformations, lowering)
- CI/build infrastructure experience
- Hardware toolchain familiarity (Yosys, Verilator, LLVM, MLIR, or similar)
- Synthesis, place and route, or static timing analysis experience
- Comfort with ambiguity and iterative user feedback
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OpenAI
OpenAI builds AI infrastructure and products, including large-scale data center campuses for AI computing and generative AI applications for enterprise customers. The company is hiring civil engineers, project engineers, electrical design engineers, data center R&D engineers, and AI deployment engineers to expand its infrastructure capabilities and help customers deploy AI solutions.
View all jobs at OpenAILikely interview questions
- Walk us through a compiler or IR-based project you've built or contributed to. How did you approach designing the representation and transformation passes?
- Describe your experience reading and reasoning about RTL (Verilog/SystemVerilog). Have you debugged tooling by inspecting generated RTL, and what was your approach?