SpaceX
ASIC/SOC DFT Engineer (Silicon Engineering)
About this role
SpaceX seeks an ASIC/SOC DFT Engineer in Austin to develop Design for Test solutions for next-generation chips powering Starlink satellites and ground infrastructure. You'll own scan insertion, ATPG analysis, and verification workflows to ensure high-quality silicon manufacturing and reliability.
What you'll do
- Evaluate design readiness for scan insertion using RTL and physical design DRC tools
- Integrate and verify DFT fabrics and IP within subsystems
- Run scan insertion through synthesis tools and optimize coverage
- Execute ATPG analysis to validate scan chain quality and coverage metrics
- Perform gate-level simulations with timing and SDF annotation
- Collaborate with physical design, ATPG, and manufacturing teams on scan coverage optimization
What they're looking for
- ASIC design flow and methodologies
- Scan insertion and DFT setup
- ATPG (Automatic Test Pattern Generation)
- Verilog/SystemVerilog
- Scripting (Python, Perl, Bash, Csh)
- Physical design and verification
- UPF (Unified Power Format)
- Formal verification and DRC rule checking
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SpaceX
SpaceX develops advanced spacecraft and satellite systems, including the Starshield government satellite constellation and Starfall re-entry cargo capsule for global delivery. The company is hiring engineers in avionics integration, software test automation, mechanical design, and hardware reliability to validate flight-critical systems and ensure mission success.
- Website
- spacex.com
Likely interview questions
- Walk us through your experience with scan insertion: what tools have you used and what coverage targets have you achieved?
- Describe a time when ATPG analysis revealed a design issue—how did you resolve it?