Physical Design Engineer, ML4PD

About this role

Tenstorrent seeks a mid- to senior-level Physical Design Engineer to optimize high-performance AI/ML chip designs across synthesis, place-and-route, and tapeout phases. You'll collaborate with cross-functional teams to balance floorplanning, timing, power, and area while building comprehensive ASIC expertise on cutting-edge silicon projects.

What you'll do

• Execute physical design tasks including synthesis, place-and-route, floorplanning, and timing closure
• Optimize chip metrics across power, performance, area, and timing in collaboration with front-end teams
• Develop and refine physical design flows using scripting and automation
• Perform timing, EM/IR, and power analysis across multiple design IPs
• Manage I/O planning, clocking distribution, and low-power implementation techniques
• Support design from implementation through signoff and tapeout phases

What they're looking for

• Synthesis and place-and-route tool expertise
• Timing, power, and signal integrity analysis
• Floorplanning and physical design methodologies
• Tcl, Perl, Shell, and Python scripting
• Low-power design techniques (power gating, multi-Vt, voltage scaling)
• Logic design fundamentals and gate/transistor-level understanding
• ASIC design flow and tapeout processes
• Collaboration across chip development disciplines

Benefits

• Competitive base and variable compensation ($100k–$500k range)
• Hybrid work arrangement with locations in Austin, Fort Collins, or Santa Clara
• Opportunity to work on industry-leading AI/ML chip architectures
• Mentorship from experienced ASIC and physical design engineers
• Exposure to complete chip development lifecycle
• Culture focused on collaboration and solving complex technical challenges